View HYB39SC256160FE-6_4112281.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

June 2007
HYB39SC256[80/16]0FE HYI39SC256[80/16]0FF
256-MBit Synchronous DRAM Green Product SDRAM
Internet Data Sheet
Rev. 1.25
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
HYB39SC256[80/16]0FE, HYI39SC256[80/16]0FF Revision History: 2007-06, Rev. 1.25 Page All 41 8 11,12 18 6 6 13 13 15 19 21 21 22 22 6 Subjects (major changes since last revision) Adapted internet edition Corrected in figure 28 (auto refresh) tRC to tRFC Corrected figure 1 Corrected block diagram Added text for Auto Refresh Command (CBR) Corrected ball DQ0 to 2,8A for data signals x16 organization Corrected data Data Signal Bus [7:0] for data signals x8 organization Corrected operation command "Power Down / Clock suspend ..." in truth table Corrected operation command "Power Down Exit" to X (WE#) Corrected text to "After the mode register is set a NOP command is required" , chapter 3.2 Corrected text to "One clock delay is required for mode entry and exit", chapter 3.4 Corrected the line "Input Capacitances: CK" in table 10, chapter 4 Corrected to A0-A12 in table 10, chapter 4 Corrected tCK MIN in table 13 Corrected CLE setup time in table 13 Corrected A6 position from H to 3H in table 3
Previous Revision: 2007-06, Rev. 1.24
Previous Revision: 2007-06, Rev. 1.23 Previous Revision: 2007-06, Rev. 1.22
Previous Revision: 2007-06, Rev. 1.21 Previous Revision: 2007-05, Rev. 1.2
Previous Revision: 2007-05, Rev. 1.11 Previous Revision: 2006-09, Rev. 1.1
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03062006-NMGU-CQ9D
2
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
1
1.1
* * * * * * * * * * *
Overview
Features
* * * * * * * Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7.8 s) Random Column Address every CLK (1-N Rule) Single 3.3 V 0.3 V Power Supply LVTTL Interface Plastic Packages - PG-TSOPII-54 (400mil width) - PG-TFBGA-54 (12 mm x 8 mm) * RoHS compliant product
This chapter lists all main features of the product family HY[B/I]39SC256[80/16]0F[E/F] and the ordering information.
Fully Synchronous to Positive Clock Edge 0 to 70 C Operating Temperature for HYB... -40 to 85 C Operating Temperature for HYI... Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read / Write control (x8, x16) Data Mask for Byte Control (x16)
TABLE 1
Performance
Product Type Speed Code Speed Grade Max. Clock Frequency @CL3 -6 PC166-333 -7 PC143-333 PC133-2221) 143 7 5.4 7.5 5.4 Unit -- MHz ns ns ns ns
@CL2
1) Max. Frequency CL/tRCD / tRP
fCK3 tCK3 tAC3 tCK2 tAC2
166 6 5.4 7.5 5.4
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
3
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
1.2
Description
output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V 0.3 V power supply. All 256-Mbit components are available in PG- TSOPII-54 and PG-TFBGA-54 packages.
The HY[B/I]39SC256[80/16]0F[E/F] are four bank Synchronous DRAM's organized as 16 MBit x8 and 8 Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda advanced 0.11 m 256-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) HYB39SC256800FE-6 HYB39SC256160FE-6 HYB39SC256800FE-7 HYB39SC256800FEH-7 HYB39SC256160FE-7 HYB39SC256160FEH-7 HYB39SC256160FF-6 HYB39SC256160FF-7 HYB39SC256800FF-7 Industrial Operating Temperature (-40 to 85 C) HYI39SC256800FE-6 HYI39SC256160FE-6 HYI39SC256800FE-7 HYI39SC256160FE-7 PC133-222 PC166-333 166MHz 16M x8 SDRAM 166MHz 8M x16 SDRAM 143MHz 16M x8 SDRAM 143MHz 8M x16 SDRAM PG-TSOPII-54
2)
Speed Grade PC166-333 PC133-222
Description 166MHz 16M x8 SDRAM 166MHz 8M x16 SDRAM 143MHz 16M x8 SDRAM 143MHz 8M x16 SDRAM
Package PG-TSOPII-54
Note
2)
Standard Operating Temperature (0 to 70 C)
PC166-333 PC133-222
166MHz 8M x16 SDRAM 143MHz 8M x16 SDRAM 143MHz 8M x8SDRAM
PG-TFBGA-54
2)
1) Please check with your Qimonda representative that leadtime and availability of your preferred device and version meet your project requirements. 2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Note: For product nomenclature see Chapter 6 of this data sheet
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
4
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
2
Configuration
This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams for the x8, x16 organization of the SDRAM.
2.1
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM
TABLE 3
Pin Configuration of the SDRAM
Pin No. Name Pin Type I I I I I I I I I I I I I I I I I I I I I Buffer Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Address Signal, Address Signal 10/Auto precharge Chip Select Bank Address Signals 1:0 Function
Clock Signals x8/x16 Organization 38,2F 37,3F 18, 8F 17, 7F 16, 9F 19, 9G 20, 7G 21, 8G 23, 7H 24, 8H 25, 8J 26, 7J 29, 3J 30, 2J 31, 3H 32, 2H 33, 1H 34, 3G 22, 9H 35, 2G 36, 1G CLK CKE RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Clock Signal CK Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Control Signals x8/x16 Organization
Address Signals x8/x16 Organization
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
5
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Pin No.
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR PWR PWR
Buffer Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL -- -- -- --
Function
Data Signals x8 Organization 2, 8A 5, 8B 8, 8C 11, 8D 44, 2D 47, 2C 50, 2B 53, 2A 2, 8A 4, 9B 5, 8B 7, 9C 8, 8C 10, 9D 11, 8D 13, 9E 42, 1E 44, 2D 45, 1D 47, 2C 48, 1C 50, 2B 51, 1B 53, 2A 39, 1F 39, 1F 15, 8E 3B, 3D, 7A, 7C 7E, 9A, 9J 3A, 3C, 7B, 7D 1J, 1A, 3E DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM UDQM LDQM VDDQ VDD VSSQ VSS Data Signal Bus [7:0]
Data Signals x16 Organization Data Signal Bus [15:0]
Data Mask x8 Organization Data Mask Data Mask Upper Byte Data Mask Lower Byte Power Supply Power Supply Power Supply Ground for DQs Power Supply Ground Data Mask x16 Organization
Power Supplies x8/x16 Organization
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
6
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Pin No.
Name
Pin Type NC
Buffer Type --
Function
Not connected x8 Organization 7, 10, 13, NC 15, 40, 42, 45, 48, 51, 1B, 1C, 1D, 1E, 2E, 8E, 9B, 9C, 9D, 9E 40, 2E NC Not connected
Not connected x16 Organization NC -- Not connected
FIGURE 1
Pin Configuration PG-TSOPII-54
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
7
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Ballout for x16 Components, PG-TFBGA-54 (top view)
FIGURE 2
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
8
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Ballout for x8 components, PG-TFBGA-54 (top view)
FIGURE 3
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
9
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
3
Functional Description
TABLE 4
Truth Table: Operation Command
This chapter lists all defined commands and their usage for this Synchronous DRAM.
Operation Bank Active Bank Precharge Precharge All Write Write with Auto precharge Read Read with Auto precharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down/ Clock Suspend Entry Power Down/ Clock Suspend Exit Data Write/ Output Enable Data Write/ Output Disable
Device State Idle3) Any Any Active3) Active
3)
CKE n-11)2) H H H H H H H H H H H H H L H L H H
CKE n1)2) X X X X X X X X X X X H L H L H X X
DQM
1)2)
BA0 BA11)2) V V X V V V V V X X X X X X X X X X
AP= A101)2) V L H L H L H V X X X X X X X X X X
Addr. CS1 RAS
1)2) )2) 1)2)
CAS1 WE
)2) 1)2)
X X X X X X X X X X X X X X X X L H
V X X V V V V V X X X X X X X X X X
L L L L L L L L L L H L L H L H L H L X X
L L L H H H H L H H X L L X H X H X H X X
H H H L L L L L H H X L L X H X H X H X X
H L L L L H H L H L X H H X X X H X H X X
Active3) Active Idle Any Active Any Idle Idle Idle (Self Refr.) Active or Idle or Burst Active or Idle or Burst Active Active
3)
1) V = Valid, x = Don't Care, L = Low Level, H = High Level 2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3) This is the state of the banks designated by BA0, BA1 signals.
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
10
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field BL Bits [2:0] Type w Description Burst Length Number of sequential bits per DQ related to one read/write command, see Table 6 Note: All other bit combinations are RESERVED 000B 001B 010B 011B 111B BT 3 1 2 4 8 Full Page (Sequential burst type only)
Burst Type Sequential 0B 1B Interleaved CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 2 011B 3
CL
[6:4]
TM
[8:7]
Test Mode Note: All other bit combinations are RESERVED. 00B Mode register set Write Burst Length 0B Burst write 1B Single bit write Reserved, set to zero
WBL
9
[12:10]
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
11
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
TABLE 6
Burst Length and Sequence
Burst Length Starting Column Address A2 2 4 0 0 1 1 8 0 0 0 0 1 1 1 1 FullPage Notes 1. 2. 3. 4. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. n 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type=Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 .... Type=Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
12
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
4
4.1
Electrical Characteristics
Operating Conditions
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Limit Values Min. Max. +4.6 +4.6 +4.6 +70 +85 +150 1 50
Unit
Note/ Test Condition
Input / Output voltage relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature for HYB... Operating Temperature for HYI... Storage temperature range Power dissipation per SDRAM component Data out current (short circuit)
VIN, VOUT VDD VDDQ TA TA TSTG PD IOUT
-1.0 -1.0 -1.0 0 -40 -55 -- --
V V V C C C W mA
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
13
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
TABLE 8
DC Characteristics
Parameter Symbol Values Min. Max. Unit Note/ Test Condition V V V V V A A
1) 1) 1)2) 1)2) 1) 1)
VDD I/O Supply Voltage VDDQ Input high voltage VIH Input low voltage VIL Output high voltage (IOUT = - 4.0 mA) VOH Output low voltage (IOUT = 4.0 mA) VOL Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL IOL Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ)
Supply Voltage
3.0 3.0 2.0 2.4 -- -5 -5
3.6 3.6
VDDQ + 0.3 V
-- 0.4 +5 +5
-0.3 +0.8
1) All voltages are referenced to VSS 2) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 9
Input and Output Capacitances
Parameter Symbol Values Min. Input Capacitances: CK Input Capacitance (A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ) 1) VDD,VDDQ = 3.3 V 0.3 V, f = 1 MHz, TA see Table 7 CI1 CI2 CI0 2.5 2.5 4.0 Max. 3.5 3.8 6.0 pF pF pF
1)2) 1)2)
Unit
Note
1)2)
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
TABLE 10
IDD Conditions
Parameter Operating Current Precharge Standby Current No Operating Current Burst Operating Current Auto Refresh Current Self Refresh Current One bank active, Burst length = 1 Power down mode Non-power down mode Active state (max. 4 banks) Read command cycling Auto Refresh command cycling Self Refresh Mode, CKE=0.2 V, tCK=infinity Symbol
IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 IDD6
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
14
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
TABLE 11
IDD Specifications and Conditions
Symbol Test Condition -6 100 2 26 40 5 65 168 25 3 -7 80 2 22 35 5 57 142 25 3 Unit mA mA mA mA mA mA mA mA mA Note 1)
2)3) 1) 1) 1) 1) 1)3) 4)
IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 IDD6
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE VIL(max) CS =VIH (min.), CKE VIH(min) CS = VIH(min), CKE VIH(min.) CS = VIH(min), CKE VIL(max.) --
tRFC= tRFC(min) tRFC= 15.6 s
--
1) VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V, TA see Table 7 2) These parameters depend on the cycle rate. All values are measured at 133 MHz for -7 with the outputs open. Input signals are changed once during tCK. 3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. 4) tRFC= tRFC(min) "burst refresh", tRFC= 15.6 s "distributed refresh".
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
15
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
4.2
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications
Parameter
Symbol
-7 PC143-333 Min. Max. -- -- 5.4 5.4 -- -- 1.2 -- -- -- -- -- 7 -- -- 100k -- -- -- -- 64 -- -- -- 7 2
-6 PC166-333 Min. 6 7.5 -- -- 2 2 0.3 1.5 0.8 1.5 0.8 2 0 15 15 36 60 60 12 1 - 1 2.5 0 3 -- Max. -- -- 5.4 5.4 -- -- 1.2 -- -- -- -- -- 6 -- -- 100k -- -- -- -- 64 -- -- -- 6 2
Unit
Note1)2)3)
Clock and Clock Enable Clock Frequency Access Time from Clock
tCK tAC
7 7.5 -- -- 2.5 2.5 0.3 1.5 0.8 1.5 0.8 2 0 15 15 37 60 63 14 1 - 1 3 0 3 --
ns ns ns ns ns ns ns ns ns ns ns
CL3 CL2 CL3 CL2
3)4)5)
Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up to Active delay Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Row Cycle Time during Auto Refresh Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Data Out Hold Time Read Cycle Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tCH tCL tT tIS tIH tCKS tCKH tRSC tSB tRCD tRP tRAS tRC tRFC tRRD tCCD tREF tSREX tOH tLZ tHZ tDQZ
6) 6) 6) 6)
tCK
ns ns ns ns ns ns ns
7) 7) 7) 7) 7)
tCK
ms
tCK
ns ns ns
3)5)
tCK
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
16
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Parameter
Symbol
-7 PC143-333 Min. Max. -- -- --
-6 PC166-333 Min. 12 -- 0 Max. -- -- --
Unit
Note1)2)3)
Write Cycle Last Data Input to Precharge (Write without Auto Precharge) Last Data Input to Activate (Write with Auto Precharge) DQM Write Mask Latency
tWR tDAL(min.) tDQW
14 -- 0
ns
8)
tCK tCK
9)
1) TA = 0 to 70 C; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V, tT = 1 ns 2) For proper power-up see the operation section of this data sheet. 3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V. 4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater or equal the specified tWR value, where tck is equal to the actual system clock time. 9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
FIGURE 4
Measurement conditions for tAC and tOH
t CH CLO C K 1 .4 V tCL t IH tT 2 .4 V 0 .4 V
t IS
IN P U T tA C t LZ OUTPUT
1 .4 V tAC tOH 1.4 V
I/O
t HZ
IO.vsd
50 pF
Measurement conditions for tAC and tOH
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
17
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
5
Package Outlines
FIGURE 5
Package Outline PG-TSOPII-54 (top view)
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
18
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
FIGURE 6
Package Outline PG-TFBGA-54-15
Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
19
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
6
Product Nomenclature
TABLE 13
Examples for Nomenclature Fields
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
Example for
Field Number 1 2 39 39 3 SC SC 4 256 256 5 80 16 6 7 0 0 8 F F 9 F E 10 -- -- 11 -6 -7
SDRAM SDRAM
HYB HYI
TABLE 14
Memory Components
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB HYI 39 SC 128 256 512 5+6 Number of I/Os 40 80 16 7 8 Product Variations Die Revision 0 .. 9 C D F 9 10 11 Package, Lead-Free Status Power Speed Grade E F - -6 -7 Coding Memory components Memory components, industrial temperature range (-40 C - +85 C) 3.3 V Single Data Rate SDRAM Consumer Product 128 Mbit 256 Mbit 512 Mbit x4 x8 x16 look up table Third Fourth Fifth TSOP, lead- and halogen-free FBGA, lead- and halogen-free Standard power product PC166-333 PC143-333, PC133-222
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
20
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Pin Configuration PG-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ballout for x16 Components, PG-TFBGA-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ballout for x8 components, PG-TFBGA-54 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outline PG-TSOPII-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package Outline PG-TFBGA-54-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
21
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Examples for Nomenclature Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
22
Internet Data Sheet
HY[B/I]39SC256[80/16]0F[E/F] 256-MBit Synchronous DRAM
Table of Contents
1 1.1 1.2 2 2.1 3 4 4.1 4.2 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Rev. 1.25, 2007-06 03062006-NMGU-CQ9D
23
Internet Data Sheet
Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

▲Up To Search▲

Price & Availability of HYB39SC256160FE-6

	To Download HYB39SC256160FE-6 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .